Candidate Subcircuit Generation to Facilitate Identification of High-Level Components in Logic Circuits

Jennifer L. White, Travis E. Doom, Anthony S. Wojcik, Moon-Jung Chung, Greg Chisholm

Research output: Working paperPreprint

Abstract

Recovering the design of a circuit involves raising the level of abstraction from a flat netlist to a more easily understood modular level. Efficient algorithms exist to locate gate clusters (subcircuits) that are syntactically equivalent to known modules, but such technology will fail to match semantically equivalent subcircuits that differ in implementation. This paper discusses the problem of generating the candidate subcircuits so that their equivalence to a known high level module can be examined.

Original languageAmerican English
StatePublished - Dec 1 1997

Disciplines

  • Computer Sciences
  • Engineering

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