Candidate subcircuits for functional module identification in logic circuits

Jennifer L. White; Anthony S. Wojcik; Moon Jung Chung; Travis E. Doom

doi:10.1145/330855.332575

Candidate subcircuits for functional module identification in logic circuits

Jennifer L. White, Anthony S. Wojcik, Moon Jung Chung, Travis E. Doom

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Recovering functional information from existing hardware is a difficult problem in design automation. However, it is an important focus for designers attempting to redesign for expanded functionality or superior performance. Often, the only reliable information available about a piece of digital hardware is the hardware itself. Documentation, even if it is available, may be outdated or incorrect. Existing procedures are able to recover the transistor-level netlist, or a gate-level netlist from an existing implementation. The next step in this process is the gate-level to module-level transformation, the focus of this paper. We have designed a technique to enumerate all of the potential modules within a gate-level netlist so that their functional equivalence to known modules may be evaluated.

Original language	English
Title of host publication	GLSVLSI '00: Proceedings of the 10th Great Lakes symposium on VLSI
Publisher	Association for Computing Machinery
Pages	34-38
Number of pages	5
ISBN (Print)	978-1-58113-251-9
DOIs	https://doi.org/10.1145/330855.332575
State	Published - Mar 2 2000
Externally published	Yes
Event	10th Great Lakes Symposium on VLSI - Chicago, IL, USA Duration: Mar 2 2000 → Mar 4 2000 Conference number: 10

Conference

Conference	10th Great Lakes Symposium on VLSI
Abbreviated title	GLSVLSI 2000
City	Chicago, IL, USA
Period	3/2/00 → 3/4/00

ASJC Scopus Subject Areas

Electrical and Electronic Engineering

Disciplines

Computer Sciences
Engineering

Access to Document

10.1145/330855.332575

Cite this

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title = "Candidate subcircuits for functional module identification in logic circuits",

abstract = " Recovering functional information from existing hardware is a difficult problem in design automation. However, it is an important focus for designers attempting to redesign for expanded functionality or superior performance. Often, the only reliable information available about a piece of digital hardware is the hardware itself. Documentation, even if it is available, may be outdated or incorrect. Existing procedures are able to recover the transistor-level netlist, or a gate-level netlist from an existing implementation. The next step in this process is the gate-level to module-level transformation, the focus of this paper. We have designed a technique to enumerate all of the potential modules within a gate-level netlist so that their functional equivalence to known modules may be evaluated.",

author = "White, \{Jennifer L.\} and Wojcik, \{Anthony S.\} and Chung, \{Moon Jung\} and Doom, \{Travis E.\}",

year = "2000",

month = mar,

day = "2",

doi = "10.1145/330855.332575",

language = "English",

isbn = "978-1-58113-251-9",

pages = "34--38",

booktitle = "GLSVLSI '00: Proceedings of the 10th Great Lakes symposium on VLSI",

publisher = "Association for Computing Machinery",

note = "10th Great Lakes Symposium on VLSI ; Conference date: 02-03-2000 Through 04-03-2000",

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T1 - Candidate subcircuits for functional module identification in logic circuits

AU - White, Jennifer L.

AU - Wojcik, Anthony S.

AU - Chung, Moon Jung

AU - Doom, Travis E.

N1 - Conference code: 10

PY - 2000/3/2

Y1 - 2000/3/2

N2 - Recovering functional information from existing hardware is a difficult problem in design automation. However, it is an important focus for designers attempting to redesign for expanded functionality or superior performance. Often, the only reliable information available about a piece of digital hardware is the hardware itself. Documentation, even if it is available, may be outdated or incorrect. Existing procedures are able to recover the transistor-level netlist, or a gate-level netlist from an existing implementation. The next step in this process is the gate-level to module-level transformation, the focus of this paper. We have designed a technique to enumerate all of the potential modules within a gate-level netlist so that their functional equivalence to known modules may be evaluated.

AB - Recovering functional information from existing hardware is a difficult problem in design automation. However, it is an important focus for designers attempting to redesign for expanded functionality or superior performance. Often, the only reliable information available about a piece of digital hardware is the hardware itself. Documentation, even if it is available, may be outdated or incorrect. Existing procedures are able to recover the transistor-level netlist, or a gate-level netlist from an existing implementation. The next step in this process is the gate-level to module-level transformation, the focus of this paper. We have designed a technique to enumerate all of the potential modules within a gate-level netlist so that their functional equivalence to known modules may be evaluated.

UR - https://www.scopus.com/pages/publications/0033723240

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UR - https://corescholar.libraries.wright.edu/cse/286

U2 - 10.1145/330855.332575

DO - 10.1145/330855.332575

M3 - Conference contribution

SN - 978-1-58113-251-9

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BT - GLSVLSI '00: Proceedings of the 10th Great Lakes symposium on VLSI

PB - Association for Computing Machinery

T2 - 10th Great Lakes Symposium on VLSI

Y2 - 2 March 2000 through 4 March 2000

ER -

Candidate subcircuits for functional module identification in logic circuits

Abstract

Conference

ASJC Scopus Subject Areas

Disciplines

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